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INTEGRATED CIRCUITS
74AVC16334A 16-bit registered driver with inverted register enable and Dynamic Controlled OutputsTM (3-State)
Product specification Supersedes data of 2000 May 02 2000 Aug 03
Philips Semiconductors
Philips Semiconductors
Product specification
16-bit registered driver with inverted register enable and Dynamic Controlled OutputsTM (3-State)
74AVC16334A
FEATURES
* Wide supply voltage range of 1.2 V to 3.6 V * Complies with JEDEC standard no. 8-1A/5/7. * CMOS low power consumption * Input/output tolerant up to 3.6 V * DCO (Dynamic Controlled Output) circuit dynamically changes
output impedance, resulting in noise reduction without speed degradation
PIN CONFIGURATION
OE Y0 Y1 GND Y2 Y3 VCC Y4 Y5 GND Y6 Y7 Y8 Y9 GND Y10 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 CP A0 A1 GND A2 A3 VCC A4 A5 GND A6 A7 A8 A9 GND A10 A11 VCC A12 A13 GND A14 A15 LE
* Low inductance multiple VCC and GND pins for minimum noise
and ground bounce
* Power off disables 74AVC16334A outputs, permitting Live * Integrated input diodes to minimize input overshoot and * Full PC133 solution provided when used with PCK2509S or
PCK2510S and CBT16292 undershoot Insertion
DESCRIPTION
The 74AVC16334A is a 16-bit universal bus driver. Data flow is controlled by output enable (OE), latch enable (LE) and clock inputs (CP). This product is designed to have an extremely fast propagation delay and a minimum amount of power consumption. To ensure the high-impedance state during power up or power down, OE should be tied to VCC through a pullup resistor (Live Insertion). A Dynamic Controlled Output (DCO) circuitry is implemented to support termination line drive during transient. See the graphs on page 8 for typical curves.
Y11 VCC Y12 Y13 GND Y14 Y15 NC
SH00167
QUICK REFERENCE DATA
GND = 0 V; Tamb = 25C; tr = tf 2.0 ns; CL = 30 pF. SYMBOL tPHL/tPLH PARAMETER Propagation delay An to Yn Propagation delay LE to Yn; CP to Yn Input capacitance Power dissipation capacitance per buffer VI = GND to VCC1 Outputs enabled Output disabled VCC = 1.8 V VCC = 2.5 V VCC = 3.3 V VCC = 1.8 V VCC = 2.5 V VCC = 3.3 V CONDITIONS TYPICAL 2.5 1.7 1.5 2.7 2.0 1.6 3.8 25 6 UNIT ns
tPHL/tPLH CI CPD
ns pF pF
NOTE: 1. CPD is used to determine the dynamic power dissipation (PD in W): PD = CPD x VCC2 x fi + S (CL x VCC2 x fo) where: fi = input frequency in MHz; CL = output load capacitance in pF; fo = output frequency in MHz; VCC = supply voltage in V; S (CL x VCC2 x fo) = sum of outputs.
ORDERING INFORMATION
PACKAGES 48-Pin Plastic Thin Shrink Small Outline (TSSOP) Type II TEMPERATURE RANGE -40C to +85C OUTSIDE NORTH AMERICA AVC16334A DGG NORTH AMERICA DRAWING NUMBER SOT362-1
2000 Aug 03
2
853-2212 24282
Philips Semiconductors
Product specification
16-bit registered driver with inverted register enable and Dynamic Controlled OutputsTM (3-State)
74AVC16334A
PIN DESCRIPTION
PIN NUMBER 24 2, 3, 5, 6, 8, 9, 11, 12, 13, 14, 16, 17, 19, 20, 22, 23 4, 10, 15, 21, 28, 34, 39, 45 7, 18, 31, 42 1 25 48 47, 46, 44, 43, 41, 40, 38, 37, 36, 35, 33, 32, 30, 29, 27, 26 SYMBOL NC Y0 to Y15 GND VCC OE LE CLK A0 to A15 NAME AND FUNCTION No connection Data outputs Ground (0 V)
LOGIC SYMBOL (IEEE/IEC)
OE CP LE 1 48 25 C3 G2 Y0 2 3 5 6 8 9 11 12 13 14 16 17 19 20 22 23 11 1 3D 47 46 44 43 41 40 38 37 36 35 33 32 30 29 27 26 A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 A10 A11 A12 A13 A14 A15 EN1 2C3
Positive supply voltage Output enable input (active LOW) Latch enable input (active LOW) Clock input Data inputs
Y1 Y2 Y3 Y4 Y5 Y6 Y7 Y8 Y9 Y10
LOGIC SYMBOL
Y11 Y12 Y13
OE
Y14 Y15
CP
SH00168
FUNCTION TABLE
INPUTS OE
LE
LE X L L H H H
CLK X X X L or H
A X L H L H X
OUTPUTS Z L H L H Y01
H L L
A1 D LE CP Y1
L L L H L X Z
SH00202
TO THE 17 OTHER CHANNELS
= = = = =
HIGH voltage level LOW voltage level Don't care High impedance "off" state LOW-to-HIGH level transition
NOTE: 1. Output level before the indicated steady-state input conditions were established.
2000 Aug 03
3
Philips Semiconductors
Product specification
16-bit registered driver with inverted register enable and Dynamic Controlled OutputsTM (3-State)
74AVC16334A
168-pin SDR SDRAM DIMM SDRAM SDRAM SDRAM SDRAM SDRAM SDRAM SDRAM SDRAM SDRAM SDRAM
BACK SIDE
SDRAM
SDRAM
SDRAM
SDRAM
SDRAM
SDRAM
SDRAM
FRONT SIDE 74AVC16334A 74AVC16334A 74AVC16334A PCK2509S or PCK2510S
The PLL clock distribution device and AVC registered drivers reduce signal loads on the memory controller and prevent timing delays and waveform distortions that would cause unreliable operation
SDRAM
SW00525
RECOMMENDED OPERATING CONDITIONS
SYMBOL VCC VCC VI VO Tamb tr, tf PARAMETER DC supply voltage (according to JEDEC Low Voltage Standards) DC supply voltage (for low voltage applications) DC Input voltage range DC output voltage range; output 3-State DC output voltage range; output HIGH or LOW state Operating free-air temperature range Input rise and fall times VCC = 1.65 to 2.3 V VCC = 2.3 to 3.0 V VCC = 3.0 to 3.6 V CONDITIONS MIN 1.65 2.3 3.0 1.2 0 0 0 -40 0 0 0 MAX 1.95 2.7 3.6 3.6 3.6 3.6 VCC +85 30 20 10 UNIT V V V V C ns/V
ABSOLUTE MAXIMUM RATINGS
In accordance with the Absolute Maximum Rating System (IEC 134). Voltages are referenced to GND (ground = 0 V). SYMBOL VCC IIK VI IOK VO VO IO IGND, ICC Tstg PTOT PARAMETER DC supply voltage DC input diode current DC input voltage DC output diode current DC output voltage; output 3-State DC output voltage; output HIGH or LOW state DC output source or sink current DC VCC or GND current Storage temperature range Power dissipation per package -plastic thin-medium-shrink (TSSOP) For temperature range: -40 to +125 C above +55C derate linearly with 8 mW/K VI t0 For data inputs1 VO uVCC or VO t 0 Note 1 Note 1 VO = 0 to VCC CONDITIONS RATING -0.5 to +4.6 -50 -0.5 to 4.6 "50 -0.5 to 4.6 -0.5 to VCC +0.5 "50 "100 -65 to +150 600 UNIT V mA V mA V V mA mA C mW
NOTE: 1. The input and output voltage ratings may be exceeded if the input and output current ratings are observed.
2000 Aug 03
4
Philips Semiconductors
Product specification
16-bit registered driver with inverted register enable and Dynamic Controlled OutputsTM (3-State)
74AVC16334A
DC ELECTRICAL CHARACTERISTICS
Over recommended operating conditions. Voltage are referenced to GND (ground = 0 V). LIMITS SYMBOL PARAMETER VCC = 1.2 V VIH HIGH level Input voltage VCC = 1.65 to 1.95 V VCC = 2.3 to 2.7 V VCC = 3.0 to 3.6 V VCC = 1.2 V VIL LOW level Input voltage VCC = 1.65 to 1.95 V VCC = 2.3 to 2.7 V VCC = 3.0 to 3.6 V VCC = 1.65 to 3.6 V; VI = VIH or VIL; IO = -100 A VOH HIGH level output voltage g VCC = 1.65 V; VI = VIH or VIL; IO = -4 mA VCC = 2.3 V; VI = VIH or VIL; IO = -8 mA VCC = 3.0 V; VI = VIH or VIL; IO = -12 mA VCC = 1.65 to 3.6 V; VI = VIH or VIL; IO = 100 A VOL LOW level output voltage g VCC = 1.65 V; VI = VIH or VIL; IO = 4 mA VCC = 2.3 V; VI = VIH or VIL; IO = 8 mA VCC = 3.0 V; VI = VIH or VIL; IO = 12 mA II IOFF Input leakage current In ut 3-State output OFF-state current VCC = 3 6 V; 3.6 VI = VCC or GND VCC = 0 V; VI or VO = 3.6 V VCC = 1.65 to 2.7 V; VI = VIH or VIL; VO = VCC or GND VCC = 3.0 to 3.6 V; VI = VIH or VIL; VO = VCC or GND VCC = 1.65 to 2.7 V; VI = VCC or GND; IO = 0 VCC = 3.0 to 3.6 V; VI = VCC or GND; IO = 0 TEST CONDITIONS Temp = -40C to +85C MIN VCC 0.65 VCC 1.7 2.0 - - - - VCC*0.20 0 20 VCC*0.45 VCC*0.55 VCC*0.70 - - - - - - - - - - TYP1 - 0.9 1.2 1.5 - 0.9 1.2 1.5 VCC VCC*0.10 VCC*0.28 VCC*0.32 GND 0.10 0.26 0.36 0.1 0.1 0.1 0.1 0.1 0.2 MAX - - - - GND 0.35 VCC 0.7 0.8 - - - - 0.20 0 20 0.45 0.55 0.70 2.5 "10 5 A 10 20 40 A A A V V V V UNIT
IO OZ
3-State 3 State output OFF state current OFF-state
ICC
Quiescent supply current
NOTE: 1. All typical values are at Tamb = 25C.
2000 Aug 03
5
Philips Semiconductors
Product specification
16-bit registered driver with inverted register enable and Dynamic Controlled OutputsTM (3-State)
74AVC16334A
AC CHARACTERISTICS
GND = 0 V; tr = tf 2.0 ns; CL = 30 pF LIMITS SYMBOL PARAMETER WAVEFORM
VCC = 3.3 0.3 V MIN TYP1 MAX VCC = 2.5 0.2 V MIN TYP1 MAX VCC = 1.8 0.15 V MIN TYP1 MAX VCC = 1.5 0.1 V MIN MAX VCC = 1.2 V TYP
UNIT
Propagation delay An to Yn tPHL/tPLH Propagation delay LE to Yn Propagation delay CP to Yn tPZH/tPZL 3-State output enable time OE to Yn 3-State output disable time OE to Yn CP pulse width HIGH or LOW LE pulse width LOW Set-up time An to CP Set-up time An to LE Hold time An to CP Hold time An to LE Maximum clock pulse frequency
1
0.7
1.5
2.6
0.8
1.7
3.0
1.0
2.5
4.4
1.7
5.3
5.0
2
0.7
1.6
3.2
1.0
2.0
3.3
1.2
2.7
4.8
1.7
6.0
5.3
ns
3
0.7
1.6
2.8
0.8
1.7
3.0
1.0
2.3
3.9
1.4
4.6
4.1
6
0.7
1.7
3.4
1.0
2.2
3.8
1.5
3.1
5.3
2.0
6.7
6.0
ns
tPHZ/tPLZ
6 3 2 5 4 5 4 3
1.0 1.0 1.0 0.2 0.4 0.6 0.4 500
2.1 - - -0.1 0.1 0.2 0.1 -
3.7 - - - - - - -
0.9 1.2 1.2 0.1 0.5 0.6 0.4 400
2.0 - - -0.1 0.1 0.2 0.1 -
3.9 - - - - - - -
1.5 2.0 2.0 0.1 0.8 0.6 0.3 250
3.7 - - -0.1 0.3 0.2 0.1 -
6.5 - - - - - - -
1.7 - - 0.1 1.2 0.6 0.3 -
7.1 - - - - - - -
6.1 -
ns
tW
ns - 0.0 ns 1.0 0.1 ns -0.4 - MHz
tS SU
th
fmax
NOTE: 1. All typical values are measured at Tamb = 25C and at VCC = 1.8 V, 2.5 V, 3.3 V.
2000 Aug 03
6
Philips Semiconductors
Product specification
16-bit registered driver with inverted register enable and Dynamic Controlled OutputsTM (3-State)
74AVC16334A
VM = 0.5 VCC VX = VOL + 0.300 V VY = VOH - 0.300 V VOL and VOH are the typical output voltage drop that occur with the output load. VI = VCC
An INPUT
GND
AC WAVEFORMS FOR VCC = 2.3 V TO 2.7 V AND VCC < 2.3 V RANGE
VM = 0.5 VCC VX = VOL + 0.15 V VY = VOH - 0.15 V VOL and VOH are the typical output voltage drop that occur with the output load. VI = VCC
VI An INPUT GND tPHL VOH tPLH VM
LE INPUT
GND NOTE: The shaded areas indicate when the input is permitted to change for predictable output performance. VM = 0.5VCC at VCC = 2.3 to 2.7 V SH00166
Waveform 4. Data set-up and hold times for the An input to the LE input
CP INPUT GND
Yn OUTPUT VOL
VM
An INPUT GND
NOTE: VM = 0.5VCC at VCC = 2.3 to 2.7 V
SH00132
Waveform 1. Input (An) to output (Yn) propagation delay
Yn OUTPUT VOL
VI LE INPUT GND VM tW VM
NOTE: The shaded areas indicate when the input is permitted to change for predictable output performance. VM = 0.5VCC at VCC = 2.3 to 2.7 V SH00136
tPHL
VOH Yn OUTPUT VOL VM
tPLH
Waveform 5. Data set-up and hold times for the An input to the clock CP input
NOTE: VM = 0.5 VCC at VCC = 2.3 to 2.7 V
nOE INPUT
SH00165
GND
Waveform 2. Latch enable input (LE) pulse width, the latch enable input to output (Yn) propagation delays.
VCC 1/fMAX VI CP INPUT GND VM tW VM OUTPUT LOW-to-OFF OFF-to-LOW
VOL tPHZ tPZH
tPHL
VOH Yn OUTPUT VOL VM
tPLH
VOH OUTPUT HIGH-to-OFF OFF-to-HIGH GND outputs enabled NOTE: VM = 0.5VCC at VCC = 2.3 to 2.7 V VY VM
NOTE: VM = 0.5VCC at VCC = 2.3 to 2.7 V
SH00135
Waveform 3. The clock (CP) to Yn propagation delays, the clock pulse width and the maximum clock frequency.
2000 Aug 03
7
EEE E EEEEEEEEEE EEE E EEEEEEEEEE EEE EEEEEEEE EEE
VI VM th th tSU tSU VI VM VI VM tsu th tsu th VI VOH VI VM
AC WAVEFORMS FOR VCC = 3.0 V TO 3.6 V RANGE
Waveform 6. 3-State enable and disable times
EEEEEEEEEEEE EE EEEEEEEEEEEE EE EEEEEEEEEEEE EE
VM tPLZ tPZL VM VX outputs disabled outputs enabled
SH00137
Philips Semiconductors
Product specification
16-bit registered driver with inverted register enable and Dynamic Controlled OutputsTM (3-State)
74AVC16334A
TEST CIRCUIT
VCC S1 2 * VCC Open GND
GRAPHS
3.5 VOL OUTPUT VOLTAGE (V) 3 2.5 2 1.5 1 0.5 0 0 50 100 150 200 250 I OL OUTPUT CURRENT (mA) VCC = 1.8 V VCC = 2.5 V VCC = 3.3 V
VI PULSE GENERATOR RT D.U.T.
VO
RL
CL
RL
Test Circuit for switching times DEFINITIONS
RL = Load resistor CL = Load capacitance includes jig and probe capacitance RT = Termination resistance should be equal to ZOUT of pulse generators.
SWITCH POSITION
TEST tPLH/tPHL tPLZ/tPZL tPHZ/tPZH S1 Open 2 < VCC
GND
SH00204
VCC < 2.3 V 2.3-2.7 V 3.0 V VI VCC VCC VCC RL 1000 500 500 VOH OUTPUT VOLTAGE (V) 3.5 3.0 2.5 2.0 1.5 1.0 V = 3.3 V 0.5 CC 0.0 -250 VCC = 2.5 V -150 VCC = 1.8 V -100 -50 0
Figure 1. Output voltage (VOL) vs. output current (IOL)
SV01018
Waveform 7. Load circuitry for switching times
-200
I OH OUTPUT CURRENT (mA)
SH00205
Figure 2. Output voltage (VOH) vs. output current (IOH) A Dynamic Controlled Output (DCO) circuit is designed in. During the transition, it initially lowers the output impedance to effectively drive the load and, subsequently, raises the impedance to reduce noise. Figures 1 and 2 show VOL vs. IOL and VOH vs. IOH curves to illustrate the output impedance and drive capability of the circuit. At the beginning of the signal transition, the DCO circuit provides a maximum dynamic drive that is equivalent to a high drive standard output device.
2000 Aug 03
8
Philips Semiconductors
Product specification
16-bit registered driver with inverted register enable and Dynamic Controlled OutputsTM (3-State)
74AVC16334A
TSSOP48: plastic thin shrink small outline package; 48 leads; body width 6.1mm
SOT362-1
2000 Aug 03
9
Philips Semiconductors
Product specification
16-bit registered driver with inverted register enable and Dynamic Controlled OutputsTM (3-State)
74AVC16334A
Data sheet status
Data sheet status Objective specification Preliminary specification Product specification Product status Development Qualification Definition [1] This data sheet contains the design target or goal specifications for product development. Specification may change in any manner without notice. This data sheet contains preliminary data, and supplementary data will be published at a later date. Philips Semiconductors reserves the right to make changes at any time without notice in order to improve design and supply the best possible product. This data sheet contains final specifications. Philips Semiconductors reserves the right to make changes at any time without notice in order to improve design and supply the best possible product.
Production
[1] Please consult the most recently issued datasheet before initiating or completing a design.
Definitions
Short-form specification -- The data in a short-form specification is extracted from a full data sheet with the same type number and title. For detailed information see the relevant data sheet or data handbook. Limiting values definition -- Limiting values given are in accordance with the Absolute Maximum Rating System (IEC 134). Stress above one or more of the limiting values may cause permanent damage to the device. These are stress ratings only and operation of the device at these or at any other conditions above those given in the Characteristics sections of the specification is not implied. Exposure to limiting values for extended periods may affect device reliability. Application information -- Applications that are described herein for any of these products are for illustrative purposes only. Philips Semiconductors make no representation or warranty that such applications will be suitable for the specified use without further testing or modification.
Disclaimers
Life support -- These products are not designed for use in life support appliances, devices or systems where malfunction of these products can reasonably be expected to result in personal injury. Philips Semiconductors customers using or selling these products for use in such applications do so at their own risk and agree to fully indemnify Philips Semiconductors for any damages resulting from such application. Right to make changes -- Philips Semiconductors reserves the right to make changes, without notice, in the products, including circuits, standard cells, and/or software, described or contained herein in order to improve design and/or performance. Philips Semiconductors assumes no responsibility or liability for the use of any of these products, conveys no license or title under any patent, copyright, or mask work right to these products, and makes no representations or warranties that these products are free from patent, copyright, or mask work right infringement, unless otherwise specified. Philips Semiconductors 811 East Arques Avenue P.O. Box 3409 Sunnyvale, California 94088-3409 Telephone 800-234-7381 (c) Copyright Philips Electronics North America Corporation 2000 All rights reserved. Printed in U.S.A. Date of release: 08-00 Document order number: 9397-750 07394
Philips Semiconductors
2000 Aug 03 10

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